Bus-type channels are often used to connect a plurality of peripheral devices, such as keyboards, printers, modems and the like, to a digital computer. Each peripheral device connected to the bus receives all of the information transmitted by the central computer but only responds to those signals on the bus which are prefixed with the device's unique address. When one of the peripheral devices has information to transmit to the central processing unit (CPU), it typically produces a low to high or logical "0" to logical "1" transition on an interrupt signal line. Such signalling is commonly referred to as active high, edge-triggered interrupt signalling. When the CPU reaches a point in its operation when it can respond to the interrupt request, it acknowledges the interrupt by sending a signal on another control line. The interrupting peripheral, upon receiving this acknowledgment signal, begins a sequence which results in the transmission of the desired information from the peripheral to the computer.
While the above-described interrupt signal routine has long been used, many computer systems were designed to only support a limited number of interrupt signal lines. This limitation can, at times, place a severe constraint on the ability of such systems to incorporate more peripheral devices. Accordingly, apparatus which permits more than one peripheral device to share a signal interrupt signal line and thereby increase the number of peripherals which can be supported would be extremely desirable.